As part of its development and strong growth, XDigit is strengthening its technical team.

As an Analog and Mixed Design Engineer, you will develop high performance analog-to-digital converter (ADC) IPs and other analog and mixed IPs that integrate new generation image sensors.

Working closely with other analog, mixed-signal and digital designers, as well as with the physical implementation engineers, you will lead the various phases of specification, IP architecture definition, design, simulation and testing.

Join the Xdigit adventure and contribute your talent to the company’s growth. The position will be based at our Grenoble site (38) or in the Bouches du Rhône (13) (Site under selection).


Your Missions

  • Lead the preliminary studies in relation with the customer and the different actors to evaluate and choose the best architectures according to the constraints of consumption, performance and surface.
  • Carry out with a high level of understanding the analysis of ADC specifications (resolution, noise spectral density, harmonic distortion, SFDR, INL, DNL) and other analog IP.
  • Carry out circuit design independently or with the support of other designers.
  • Participate in internal design reviews as well as external technical discussions with customers by being the technical guarantor of the circuit performance according to the specifications.
  • Participate in characterization and testing.
  • Support and challenge the junior analog designers during the different phases of the projects, and share your experience with them.


Your profile

  • Engineering degree, Master’s degree or PhD with at least 5 years of experience in the design and evaluation of analog functions.
  • Experience in the design of mixed-signal functions such as amplifiers, comparators, ADCs and/or DACs is mandatory.
  • Experience with Nyquist-Rate ADCs such as Pipeline or SAR architectures would be a plus.
  • Good understanding of mismatch, crosstalk, noise and power management.
  • Very good knowledge of cadence design tools, Synopsys and Siemens EDA.
  • Experience with high-level mixed-signal simulations using Cadence, Mathlab, ModelSim, including high-level ADC behavioral model simulations.
  • Good level of English necessary for communication with suppliers and customers.
  • Knowledge of VHDL, Verilog, SystemVerilog and C/C++ languages.
  • Curiosity, autonomy and organization in your work.
  • Result-oriented and customer satisfaction.
  • Ability to lead a team throughout a project.
  • A good ability to share and transfer information and knowledge.
  • Pro-active and proactive in solving problems and improving existing processes.


Salary and Package

  • Fixed salary according to profile (Syntec Convention).
  • 10 days of annual leave.
  • Meal tickets.
  • Mutual insurance.
  • 1 to 2 days of telecommuting per week.