Context of the mission
As part of its development and strong growth, XDigit is strengthening its technical team.
As a senior digital design engineer, you will study, specify, model, simulate and verify digital blocks and subsystems.
In close collaboration with the other digital designers, as well as the physical implementation engineers, you drive the different phases of specification, definition of the architecture of the digital blocks, design, simulation and testing.
Join the XDigit adventure and contribute your talent to the company’s growth. The position will be based at our Grenoble site (38) or in the Bouches du Rhône (13) (Site under selection).
Main tasks
- Write the low level specifications of the blocks to be developed.
- Estimate the costs and schedules for the development of digital blocks.
- Realize the system modeling
- Perform RTL coding (VHDL/Verilog)
- Write the specifications of the validation plan of the designed blocks.
- Develop the testbenchs (systemVerilog/SystemC/VHDL/Verilog … )
- Perform validation by simulation and code coverage.
- Define timing and consumption constraints, in interaction with the routing placement.
- Carry out performance verification tasks for the block: coverage rate, frequency, maximum consumption, area.
- Perform numerical synthesis by deploying associated techniques (DfT, scan compression, built-in self-test (BIST), JTAG …)
- Write design reports (specification review)
- Participate in characterization and testing.
- Improve the verification flow of the digital design, functional modes and test modes.
- Participate in internal design reviews as well as external technical discussions with customers by being the technical guarantor of the circuit performance according to the specifications.
- Support and challenge the junior digital designers during the different phases of the projects, and share your experience with them.
Your profile
- Engineering degree, Master’s degree or PhD with at least 5 years of experience in digital circuit design and evaluation.
- Knowledge of systemC would be a plus.
- Mastery of digital simulation and synthesis tools.
- Knowledge of formal proof tools and ATPG pattern generation would be a plus.
- Mastery of VHDL, Verilog, SystemVerilog and C/C++ languages.
- Good level of English necessary to communicate with suppliers and customers.
- Curiosity, autonomy and organization in your work.
- Result-oriented and customer satisfaction.
- Ability to lead a team throughout a project.
- A good ability to share and transfer information and knowledge.
- Proactive and proactive in solving problems and improving existing processes.
Salary and package
- Fixed salary according to profile (Syntec Convention)
- 10 days of annual leave
- Health insurance
- Meal tickets.
- 1 to 2 days of telecommuting per week.